In recent years, downsizing and cost reduction of an electronic device are demanded. For such a demand, there has been developed a technique for flip-chip mounting a plurality of device chips on a wiring substrate through bumps and sealing the device chips (see e.g. Japanese Patent Application Publication No. 2003-347483 and Japanese National Publication of International Patent Application No. 2006-513564).
When the device chips are sealed with a resin, for example, airtightness and heat dissipation deteriorate and hence reliability is damaged. Moreover, when a gap which exposes the bumps exists between the device chips and the wiring substrate, since respective thermal expansion coefficients of the wiring substrate, the device chips and a sealing unit are different from each other, a stress occurs in the bumps corresponding to the respective device chips and hence reliability is damaged.